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Fanxiang S660 2 TB

2 TB
Capacity
MAP1608A-F3C
Controller
TLC
Flash
PCIe 4.0 x4
Interface
M.2 2280
Form Factor
Front
SSD Controller
Controller
NAND Die
NAND Die
The Fanxiang S660 is a solid-state drive in the M.2 2280 form factor, launched in 2023. It is available in capacities ranging from 250 GB to 2 TB. This page reports specifications for the 2 TB variant. With the rest of the system, the Fanxiang S660 interfaces using a PCI-Express 4.0 x4 connection. The SSD controller is the MAP1608A-F3C from MaxioTech, a DRAM cache is not available. Fanxiang has installed 128-layer TLC NAND flash on the S660, the flash chips are made by YMTC. To improve write speeds, a pseudo-SLC cache is used, so bursts of incoming writes are soaked up more quickly. Thanks to support for the fast PCI-Express 4.0 interface, performance is excellent. The S660 is rated for sequential read speeds of up to 4,800 MB/s and 4,200 MB/s write.
The SSD's price at launch is unknown. The warranty length is set to five years, which is an excellent warranty period. Fanxiang guarantees an endurance rating of 1400 TBW, a typical value for consumer SSDs.

Solid-State-Drive

Capacity: 2 TB (2000 GB)
Variants: 250 GB 500 GB 1 TB 2 TB
Overprovisioning: 185.4 GB / 10.0 %
Production: Active
Released: 2023
Part Number: Unknown
Market: Consumer

Physical

Form Factor: M.2 2280 (Single-Sided)
Interface: PCIe 4.0 x4
Protocol: NVMe 1.4
Power Draw: Unknown

Controller

Manufacturer: MaxioTech
Name: MAP1608A-F3C
Architecture: ARM 32-bit Cortex-R5
Core Count: Quad-Core
Foundry: TSMC
Process: 12 nm
Flash Channels: 4 @ 1,600 MT/s
Chip Enables: 4
Controller Features: HMB (enabled)

NAND Flash

Manufacturer: YMTC
Name: Xtacking 2.0 (CDT1B)
Type: TLC
Technology: 128-layer
Speed: 1600 MT/s
Capacity: 4 chips @ 4 Tbit
ONFI: 4.1
Topology: Charge Trap
Die Size: 60 mm²
(8.5 Gbit/mm²)
Dies per Chip: 8 dies @ 512 Gbit
Planes per Die: 4
Decks per Die: 2
Word Lines: 141 per NAND String
90.8% Vertical Efficiency
Read Time (tR): 50 µs
Program Time (tProg): 620 µs
Block Erase Time (tBERS): 20 ms
Die Read Speed: 1280 MB/s
Die Write Speed: 70 MB/s
Endurance:
(up to)		 3000 P/E Cycles
Page Size: 16 KB
Block Size: 2304 Pages
Plane Size: 1980 Blocks

DRAM Cache

Type: None
Host-Memory-Buffer (HMB): 40 MB

Performance

Sequential Read: 4,800 MB/s
Sequential Write: 4,200 MB/s
Random Read: Unknown
Random Write: Unknown
Endurance: 1400 TBW
Warranty: 5 Years
Drive Writes Per Day (DWPD): 0.4
SLC Write Cache: Yes

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • Unknown
RGB Lighting: No
PS5 Compatible: Yes

Notes

Controller:

Same design as the MAP1602 but only has 4 channels @ 1600 MT/s instead of 2400 MT/s

NAND Die:

Read Time (tR): Maximum is 50 µs, typical is lower
Typical Program Time (tPROG): 620 µs
Maximum Program Time (tPROG): Maximum is 910 µs
Block Erase Time (tBERS): Maximum is 20 ms, typical is lower
Array Eficiency of over 92%
YMTC 128L Xtacking 2.0 cell architecture consists of two decks connected through deck-interface buffer layer which is the same process with KIOXIA 112L BiCS 3D NAND structure. Cell size, CSL pitch, and 9-hole VC layouts keep the same design and dimension (horizontal/vertical WL and BL pitches) with previous 64L Xtacking 1.0 cell. Total number of gates is 141 (141T) including selectors and dummy WLs for the TLC operation.
This layout has a 1x 4 Plane layout, each one lineup side by side
May 17th, 2024 12:11 EDT change timezone

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